💡
The Basics in Plain English: How the CPU Actually Works
The Central Processing Unit (CPU) is the computer's engine. Every second, it repeats the Fetch-Decode-Execute cycle billions of times: fetching an instruction from memory, decoding what it means, and executing it.
The Desk Analogy (Registers vs RAM): RAM is like a massive library down the street—it holds everything, but fetching from it takes time. Registers are like sticky notes right on your desk. Ultra-fast, but each only holds one tiny piece of data.
Key Registers to Remember:
• PC (Program Counter): Address of the NEXT instruction.
• MAR: Address of where in RAM we are reading/writing.
• MDR: Holds the actual data/instruction being moved.
• ACC (Accumulator): Holds temporary calculation results.
• PC (Program Counter): Address of the NEXT instruction.
• MAR: Address of where in RAM we are reading/writing.
• MDR: Holds the actual data/instruction being moved.
• ACC (Accumulator): Holds temporary calculation results.
Central Processing Unit (CPU)
Silicon Core
Control Unit (CU)
DECODER
Decodes instructions, directs data flow, and generates timing signals across control lines.
Decoded: NONE
Arithmetic Logic Unit (ALU)
MATH & LOGIC
Executes arithmetic calculations (+, −) and boolean logical comparisons.
ALU Result: 0
Core Registers (AQA §3.4.1)
Internal Bus
PC
Prog Counter
00
MAR
Mem Address
00
MDR
Mem Data
---
CIR
Cur Instruction
---
ACC
Accumulator
0
L1 CACHE (On-Chip SRAM)
IDLE
Hits: 0 | Misses: 0
L0
--
Empty
L1
--
Empty
L2
--
Empty
L3
--
Empty
Address Bus
Unidirectional (CPU ➔ RAM)
══════════▶
Idle
Data Bus
Bidirectional (CPU ⇄ RAM)
◀══════════▶
Idle
Control Bus
Control Signals & Clock
════⚡═════▶
Idle
Main Memory (RAM)
8 Words
| Addr | Contents | Type |
|---|
Von Neumann Principle: Data and instructions share the same memory and bus structure.
FETCH STAGE
Copy Address from PC to MAR
The memory address of the next instruction stored in the Program Counter (PC) is copied into the Memory Address Register (MAR) via the internal bus.
💡 AQA Exam Phrasing: "The address in the PC is copied to the MAR."
Execution History Log
Chronological order
1. Clock Speed (GHz)
2.5 GHz
Cycles per second (F-D-E cycles/sec)
1.0 GHz (1B cycles/s)
4.0 GHz (4B cycles/s)
2. Cache Memory Level
Extremely fast SRAM built directly on the CPU chip
3. Number of CPU Cores
Independent processing units sharing the memory bus
Select Benchmark Workload:
• Sequential tasks cannot be divided across cores. Additional cores will remain idle!
Execution Time
-
Lower is faster
Effective Speed
-
MIPS Throughput
Cache Hit Rate
-
avoided RAM stall
Power & Heat
Moderate
Thermal limits
Core Utilization:
⚠️ AQA Exam Rule (Why 2× cores does NOT mean 2× speed):
- Software must be written to support parallel multithreading. Sequential algorithms cannot use extra cores.
- CPU cores must communicate and coordinate, adding management overhead.
- All cores compete for access to the same shared memory bus and cache.
📌 Key Exam Traps & Core Concepts
AQA TRAP 1: REGISTERS
Never Confuse the MAR and the MDR
This is one of the most frequently lost marks on GCSE Computer Science papers. Remember their exact roles:
MAR (Memory Address Register):
• Holds the memory address (location) where data or an instruction is to be fetched from or written to.
• Connected to the Address Bus.
• Holds the memory address (location) where data or an instruction is to be fetched from or written to.
• Connected to the Address Bus.
MDR (Memory Data Register):
• Holds the actual data value or instruction that has been read from RAM or is waiting to be written to RAM.
• Connected to the Data Bus.
• Holds the actual data value or instruction that has been read from RAM or is waiting to be written to RAM.
• Connected to the Data Bus.
💡 Memory Hook: MAR = Address (where to look); MDR = Data (what was found).
AQA TRAP 2: CPU PERFORMANCE
Why More Cores Does Not Guarantee Faster Performance
A common exam question asks why a quad-core CPU will not run four times faster than a single-core CPU:
• Software Parallelism: Many programs are written sequentially (Step 2 depends on Step 1). Extra cores remain idle if software cannot be split into concurrent threads.
• Overhead & Communication: The operating system must coordinate and synchronise threads across cores, consuming clock cycles.
• Resource Contention: All cores share the same memory bus and RAM. Accessing RAM creates a bottleneck.
• Overhead & Communication: The operating system must coordinate and synchronise threads across cores, consuming clock cycles.
• Resource Contention: All cores share the same memory bus and RAM. Accessing RAM creates a bottleneck.
AQA SPECIFICATION §3.4.1
The Stored Program Concept (Von Neumann)
The foundation of all modern general-purpose computing systems:
✓ AQA Definition: In the Von Neumann architecture, both program instructions and data are stored together in the same physical memory (RAM) and fetched across shared system buses. Instructions are executed sequentially unless an explicit branch occurs.
📝 AQA Past Paper Style Questions with Mark Schemes
F-D-E Cycle • 4 Marks
Q1: Describe the role of the Program Counter (PC) and the Memory Address Register (MAR) during the fetch stage of the fetch-decode-execute cycle.
[1 mark]
The Program Counter (PC) holds the address of the next instruction to be fetched from memory.
[1 mark]
The address stored in the PC is copied into the Memory Address Register (MAR).
[1 mark]
The PC is incremented by 1 (to point to the subsequent instruction).
[1 mark]
The MAR places the memory address on the Address Bus to locate the instruction in RAM.
Performance • 3 Marks
Q2: A computer manufacturer claims that an 8-core CPU will execute programs four times faster than a dual-core (2-core) CPU with the same clock speed. Explain why this claim is not true in practice.
[1 mark]
Software may not be optimised for multi-threading / tasks may be sequential where one step requires the result of a previous step.
[1 mark]
Core management / coordination overhead from the operating system reduces efficiency.
[1 mark]
Shared hardware bottlenecks: all cores must share access to memory bus and RAM, causing waiting/stalls.
Hardware • 3 Marks
Q3: Explain what cache memory is and why having more cache memory improves CPU performance.
[1 mark]
Cache is very fast, small memory located on (or extremely close to) the CPU chip.
[1 mark]
It stores frequently or recently used instructions and data.
[1 mark]
Accessing cache is much faster than fetching from RAM, reducing CPU idle waiting time.